The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a gate-all-around semiconductor structure including a stack of suspended semiconductor nanowires that have a uniform shape and dimension and a method of forming the same.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, gate-all-around semiconductor nanowire field effect transistors is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices.
In its basic form, gate-all-around semiconductor nanowire field effect transistors include at least one semiconductor nanowire including a source region, a drain region and a channel region located between the source region and the drain region, and a gate electrode that wraps around the channel region of the at least one semiconductor nanowire. A gate dielectric is typically disposed between the channel region of the at least one semiconductor nanowire and the gate electrode. The gate electrode regulates electron flow through the semiconductor nanowire channel between the source region and the drain region.
Gate-all-around semiconductor nanowire field effect transistors can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. Stacked semiconductor nanowires, in which the semiconductor nanowires are formed one atop another, afford higher density than their non-stacked semiconductor nanowire counterparts.
In the fabrication of semiconductor nanowires, it is very challenging to produce semiconductor nanowires that have a desired shape and dimension. This challenge is further compounded when stacked semiconductor nanowires are fabricated. Another issue in fabricating gate-all-around semiconductor nanowire field effect transistors having stacked semiconductor nanowires is the suspension of each stacked semiconductor nanowire.
In view of the above, there is a need for providing gate-all-around semiconductor nanowire field effect transistors in which a stack of suspended semiconductor nanowires is provided in which each semiconductor nanowire has a same shape and a same dimension (i.e., height and width).